The Serial Peripheral Interface (SPI) is the signaling method of choice for efficiently communicating between a processor and a slave hardware device where “streams” of data are transferred between the devices. The SPI is a serial interface standard established by Motorola, Inc. (now Freescale Semiconductor, Inc.) and is supported in silicon products by several manufacturers. It is attractive since it requires minimum I/O pins, and allows different devices to implement software communication protocols to be constructed on top of this signaling protocol. FIG. 1 illustrates the basic prior-art SPI signaling protocol. The chip select signal (CS) is used to address a particular slave device, the master data output signal (SDI) is serial data transferred from the master to the slave on each serial clock, the master data input signal (SDO) is serial data transferred from the slave to the master, and the serial clock (SCLK) provides the clocking for the transfer. The meaning of each bit or field of bits in transferred data is application defined, and can be commands, status, addresses, or data in a predefined sequence.
In the signal processing domain, the master device is typically a Digital Signal Processor (DSP), a microprocessor, or a microcontroller, and the slave device is often a single or multi-channel analog-to-digital converter (ADC) or ADC with on-board filtering. The most used operational mode for single channel or low data-rate multiple channel devices is synchronous control. The DSP selects a device, sends a command, and provides the clocks for the slave to execute the command and send the resulting data and status back to the processor. For asynchronous multiple channel devices, allowing the devices to operate autonomously and then request output data transfers via an interrupt to the processor is a more efficient use of processing power. The high overhead associated with interrupt processing is costly, however, if there are a significant number of autonomous device channels having a high rate of data transfers. Therefore, an asynchronous control protocol that maximizes the data transferred while minimizing interrupts is preferred.
Additional signals are often added to the interface for convenience. FIG. 1 shows a common prior-art interface between a processor and multiple ADC channels. The processor starts multiple-channel data conversion by sending a signal, perhaps by sending an enable bit via the SDI pin with the appropriate channel selected by the CSn signal. When the conversion is complete, the ADC acknowledges data ready (RDY) and, using an interrupt or polling routine, the processor recognizes data ready and controls the SPI bus to transfer the appropriate number of bits in the sample. If each ADC channel is operating at different sample rates, the processor must control each channel independently, and suffer the increased overhead for polling or interrupt handling. The processor must also handle each data sample independently.